你好! Shipping to Taiwan with premium packaging for just NT$300 

Ship to
Taiwan
0
  • argentina
  • chile
  • colombia
  • españa
  • méxico
  • perú
  • estados unidos
  • internacional

Select your country

Americas

Europe

Rest of the world

portada Digital CMOS Circuit Design
Type
Physical Book
Publisher
Language
English
Pages
384
Format
Paperback
Dimensions
23.4x15.6x2 cm
Weight
0.54 kg.
ISBN13
9781461294092

Digital CMOS Circuit Design

Silvia Annaratone (Author) · Springer · Paperback

Digital CMOS Circuit Design - Annaratone, Silvia

Cheaper New Book Imported to Taiwan
Delivery: 16 Nov - 27 Nov Shipping: 14 to 18 business days.
NT$ 1,862
Faster New Book Imported to Taiwan
Delivery: 03 Nov - 11 Nov Shipping: 5 to 6 business days.
NT$ 2,347
NT$ 1,862

Synopsis "Digital CMOS Circuit Design"

In light of decreasing feature size and greater sophistication of modern processing technology, CMOS has become increasingly attractive, pro- viding low-power (at moderate frequencies), good scalability, and rail-to- rail operation. For many designers, particularly those approaching VLSI from a system viewpoint, previous experience has been mainly with ratioed NMOS design, and so there is a need to buildon this experienceand make a naturaltransition into CMOS design. Indeed, there ismuch that can bebor- rowed from NMOS experience, mainly centered around the techniques for creating N channel pulldown structures. Based on these contributions, CMOS has now grown to the point where there are several circuit styles which have evolved, and these are amply described in this book. Starting at the level ofthe individual MOSFET, basic building blocks are described, as well as the variety of CMOS fabrication processes in contemporary usage. Circuit style issues are then expandedto providethe user with several useful design methodologies, andmuchcareisgiventoelectricalperformancecon- siderations, including characteristics of interconnect, gate delay, and I/O buffering. This understanding is then applied to macro-sized components, including array multipliers, where the reader acquires a unified view of ar- chitectural performance through parallelism, and circuit performance through scrupulousattentionto device sizingandcontrolofparasiticcircuit elements. In addition, layout techniques to avoid latchup, a consideration not previously encountered by NMOS designers, are given careful treatment.

Customers reviews

Frequently Asked Questions about the Book

All books in our catalog are Original.
The book is written in English.
The binding of this edition is Paperback.

Questions and Answers about the Book

Do you have a question about the book? Login to be able to add your own question.

Opinions about Bookdelivery

More customer reviews