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portada Efficient Test Data Compression and Fault Analysis in VLSI Circuits
Type
Physical Book
Author
Publisher
Language
English
Pages
84
Format
Paperback
Dimensions
22.9x15.2x0.5 cm
Weight
0.14 kg.
ISBN13
9786138834304
Categories

Efficient Test Data Compression and Fault Analysis in VLSI Circuits

Sivaganesan Subramaniam (Author) · Scholars' Press · Paperback

Efficient Test Data Compression and Fault Analysis in VLSI Circuits - Subramaniam, Sivaganesan

New Book Imported to Taiwan
Delivery: 15 Oct - 23 Oct Shipping: 13 to 14 business days.
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NT$ 1,749

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Synopsis "Efficient Test Data Compression and Fault Analysis in VLSI Circuits"

In higher order SOC (System On Chip) circuit, designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. In this, testable input data (test data) is generated by using Automatic test pattern generation (ATPG) then it is compressed and compressed data stored to memory. To test the particular circuit that time we will decompress the stored memory test data and then decompressed test data given to the Design Under Test (DUT). Finally DUT fault is tested and identified. It proposes a test compression technique using efficient dictionary selection and bitmask method to significantly reduce the testing time and memory requirements. This algorithm giving a best possible test compression of 92% when compared with other compression methods.

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