你好! Shipping to Taiwan with premium packaging for just NT$300 

Ship to
Taiwan
0

My Account

  • argentina
  • chile
  • colombia
  • españa
  • méxico
  • perú
  • estados unidos
  • internacional

menu

Select your country

Americas

Europe

Rest of the world

portada retargetable processor system integration into multi-processor system-on-chip platforms
Type
Physical Book
Author
Publisher
Year
2010
Language
English
Pages
162
Format
Paperback
Dimensions
23.4x15.6x1 cm
Weight
0.26 kg.
ISBN
9048179165
ISBN13
9789048179169
Categories

retargetable processor system integration into multi-processor system-on-chip platforms

Andreas Wieferink (Author) · Heinrich Meyr (Author) · Rainer Leupers (Author) · Springer · Paperback

retargetable processor system integration into multi-processor system-on-chip platforms - Wieferink, Andreas ; Meyr, Heinrich ; Leupers, Rainer

Cheaper New Book Imported to Taiwan
Delivery: 30 Oct - 12 Nov Shipping: 14 to 18 business days.
NT$ 3,368
Faster New Book Imported to Taiwan
Delivery: 19 Oct - 27 Oct Shipping: 5 to 6 business days.
NT$ 4,313
NT$ 3,368

Choose the list to add your product or create one New List

Go to My Wishlists
Calculate shipping cost

Synopsis "retargetable processor system integration into multi-processor system-on-chip platforms"

Foreword. Preface. 1. INTRODUCTION. 1.1 Challenge: From Board to SoC. 1.2 Degrees of SoC Customization. 1.3 Organization of this Book. 2. SOC DESIGN METHODOLOGIES. 2.1 Traditional HW/SW Co-Design. 2.2 System Level Design. 2.3 Current Research on SoC Design Methodologies. 2.4 Contribution of this Work. 3. COMMUNICATION MODELING. 3.1 Transaction Level Modeling. 3.2 Generic Communication Modeling. 3.3 Communication Customization. 3.4 The BusCompiler Tool. 4. PROCESSOR MODELING. 4.1 Generic Processor Modeling. 4.2 Processor Customization Techniques. 4.3 LISA. 5. PROCESSOR SYSTEM INTEGRATION. 5.1 Simulator Structure. 5.2 Adaptors: Bridging Abstraction Gaps. 5.3 Commercial SoC Simulation Environments. 6. SUCCESSIVE TOP-DOWN REFINEMENT FLOW. 6.1 Phase 1: Standalone. 6.2 Phase 2: IA ASIP - AVF Communication Models. 6.3 Phase 3: IA ASIP - CA TLM Bus. 6.4 Phase 4: CA ASIP - CA TLM Bus. 6.5 Phase 5: BCA ASIP - CA TLM Bus. 6.6 Phase 6: RTL ASIP - CA TLM Bus. 6.7 Phase 7: RTL ASIP - RTL Bus. 7. AUTOMATIC RETARGETABILITY. 7.1 MP-SoC Simulator Generation Chain. 7.2 Structure of the Generated Simulator. 7.3 Bus Interface Specification. 8. DEBUGGING AND PROFILING. 8.1 Multiprocessor Debugger. 8.2 TLM Bus Traffic Visualization. 8.3 Bus Interface Analysis. 9. CASE STUDY. 9.1 Multi Processor JPEG Decoding Platform. 9.2 Phase 2: IA+AVF Platform. 9.3 Phase 3: IA + BusCompiler Platform. 9.4 Phase 4: CA + BusCompiler Platform. 9.5 Phase 5: BCA + BusCompiler Platform. 10. SUMMARY. Appendices. A. Businterface Definition Files. A.1 Generic AMBA 2.0 Protocol. A.2 Derived AMBA 2.0 Protocols. A.3 AMBA 2.0 Bus Interface Specification. B. Extended CoWare Tool Flow. List of Figures. References. Index.

Customers reviews

More customer reviews
  • 0% (0)
  • 0% (0)
  • 0% (0)
  • 0% (0)
  • 0% (0)

Frequently Asked Questions about the Book

Is the book original?

All books in our catalog are Original.

In what language is the book written?

The book is written in English.

What is the format of this book?

The binding of this edition is Paperback.

Questions and Answers about the Book

Do you have a question about the book? Login to be able to add your own question.

Opinions about Bookdelivery

More customer reviews