Name: Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS
SKU: 56773282
Price: 3351.00 TWD
Availability: InStock
Author: Noia, Brandon ; Chakrabarty, Krishnendu
ISBN: 9783319345345

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portada Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS

Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS

Type

Physical Book

Author

Krishnendu Chakrabarty

Brandon Noia

Publisher

Springer

Language

English

Pages

245

Format

Paperback

ISBN13

9783319345345

Synopsis "Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS"

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

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Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS - Noia, Brandon ; Chakrabarty, Krishnendu

Synopsis "Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS"

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