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portada An Introduction to Risc v. "Reduced Instruction set Computer" Processor
Type
Physical Book
Publisher
Author
Language
English
Pages
38
Format
Paperback
ISBN13
9783389028421

An Introduction to Risc v. "Reduced Instruction set Computer" Processor

Arpita Patel (Author) · Grin Verlag · Paperback

An Introduction to Risc v. "Reduced Instruction set Computer" Processor - Arpita Patel

New Book Imported to Taiwan
Delivery: 23 Sep - 01 Oct Shipping: 14 to 15 business days.
NT$ 834
NT$ 834

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Synopsis "An Introduction to Risc v. "Reduced Instruction set Computer" Processor"

Document from the year 2024 in the subject Computer Science, grade: A, language: English, abstract: RISC-V, an open-source Instruction Set Architecture (ISA), has become a significant performer in the realm of computer architecture, challenging traditional proprietary designs and opening the doors for innovation and customization. Initially in this work, RISC-V's historical evolution, its architecture, including its design concepts, instruction set, register file and implementations, were understood through a literature survey.A comprehensive literature survey is conducted on various variants of RISC-V family and their applications, which include lowering total costs, speeding up processor execution, consuming less power, and creating a more manageable and compact versions of the original architecture. The study includes a thorough analysis of several RISC-V variations. According to review of the literature, the 32-bit biRISC-V processor core is the newest member of the RISC-V family and using superscalar dual issue design to increase processor overall throughput.

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