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portada Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS
Type
Physical Book
Author
Publisher
Language
English
Pages
245
Format
Hardcover
Dimensions
23.4x15.2x2 cm
Weight
0.66 kg.
ISBN13
9783319023779
Edition No.
2014th
Categories

Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS

Krishnendu Chakrabarty (Author) · Brandon Noia (Author) · Springer · Hardcover

Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS - Noia, Brandon ; Chakrabarty, Krishnendu

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Synopsis "Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS"

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

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