Name: direct transistor-level layout for digital blocks
SKU: 3405003
Price: 3406.00 TWD
Availability: InStock
Author: gopalakrishnan,rutenbar

portada direct transistor-level layout for digital blocks

direct transistor-level layout for digital blocks

Type

Physical Book

Publisher

Springer

Author

gopalakrishnan,rutenbar

Language

English

Pages

180

ISBN

1402076657

ISBN13

9781402076657

Synopsis "direct transistor-level layout for digital blocks"

cell-based design methodologies have dominated layout generation of digital circuits. unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. direct transistor-level layout for digital blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. this approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. the key idea is early identification of essential diffusion-merged mos device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. the essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. individual transistors may seem simple, but they do not pack as gates do. algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. the approach described in this book can pack devices much more densely than a typical cell-based layout.direct transistor-level layout for digital blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to cad tool and circuit designers.