你好! Shipping to Taiwan with premium packaging for just NT$300 

Ship to
Taiwan
0

My Account

  • argentina
  • chile
  • colombia
  • españa
  • méxico
  • perú
  • estados unidos
  • internacional

menu

Select your country

Americas

Europe

Rest of the world

portada Finite State Machine Datapath Design, Optimization, and Implementation
Type
Physical Book
Author
Publisher
Language
English
Pages
113
Format
Paperback
ISBN13
9783031797750
Edition No.
1
Categories

Finite State Machine Datapath Design, Optimization, and Implementation

Justin Davis (Author) · Robert Reese (Author) · Springer · Paperback

Finite State Machine Datapath Design, Optimization, and Implementation - Davis, Justin ; Reese, Robert

Cheaper New Book Imported to Taiwan
Delivery: 16 Oct - 26 Oct Shipping: 15 to 16 business days.
NT$ 1,284
Faster New Book Imported to Taiwan
Delivery: 14 Oct - 22 Oct Shipping: 13 to 14 business days.
NT$ 1,471
NT$ 1,284

Choose the list to add your product or create one New List

Go to My Wishlists
Calculate shipping cost

Synopsis "Finite State Machine Datapath Design, Optimization, and Implementation"

Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL. Table of Contents: Calculating Maximum Clock Frequency / Improving Design Performance / Finite State Machine with Datapath (FSMD) Design / Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs

Customers reviews

More customer reviews
  • 0% (0)
  • 0% (0)
  • 0% (0)
  • 0% (0)
  • 0% (0)

Frequently Asked Questions about the Book

Is the book original?

All books in our catalog are Original.

In what language is the book written?

The book is written in English.

What is the format of this book?

The binding of this edition is Paperback.

Questions and Answers about the Book

Do you have a question about the book? Login to be able to add your own question.

Opinions about Bookdelivery

More customer reviews