Tracked shipping to Taiwan with premium packaging for just NT$300 

Ship to
Taiwan
0
  • argentina
  • chile
  • colombia
  • españa
  • méxico
  • perú
  • estados unidos
  • internacional

Select your country

Americas

Europe

Rest of the world

portada Processor Microarchitecture: An Implementation Perspective
Type
Physical Book
Publisher
Language
English
Pages
106
Format
Paperback
Dimensions
23.5 x 19.1 x 0.6 cm
Weight
0.22 kg.
ISBN13
9783031006012

Processor Microarchitecture: An Implementation Perspective

Fernando Latorre (Author) · Antonio Gonzalez (Author) · Grigorios Magklis (Author) · Springer · Paperback

Processor Microarchitecture: An Implementation Perspective - Gonzalez, Antonio ; Latorre, Fernando ; Magklis, Grigorios

Cheaper New Book Imported to Taiwan *
Delivery: 29 Apr - 15 May Shipping: 11 to 18 business days.
NT$ 1,409
Faster New Book Imported to Taiwan *
Delivery: 14 Apr - 22 Apr Shipping: 2 to 3 business days.
NT$ 1,442
NT$ 1,409
Delivery to any Taiwan address between Wednesday, April 29 and Friday, May 15

Synopsis "Processor Microarchitecture: An Implementation Perspective"

This lecture presents a study of the microarchitecture of contemporary microprocessors. The focus is on implementation aspects, with discussions on their implications in terms of performance, power, and cost of state-of-the-art designs. The lecture starts with an overview of the different types of microprocessors and a review of the microarchitecture of cache memories. Then, it describes the implementation of the fetch unit, where special emphasis is made on the required support for branch prediction. The next section is devoted to instruction decode with special focus on the particular support to decoding x86 instructions. The next chapter presents the allocation stage and pays special attention to the implementation of register renaming. Afterward, the issue stage is studied. Here, the logic to implement out-of-order issue for both memory and non-memory instructions is thoroughly described. The following chapter focuses on the instruction execution and describes the different functional units that can be found in contemporary microprocessors, as well as the implementation of the bypass network, which has an important impact on the performance. Finally, the lecture concludes with the commit stage, where it describes how the architectural state is updated and recovered in case of exceptions or misspeculations. This lecture is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture. It is also intended for practitioners in the industry in the area of microprocessor design. The book assumes that the reader is familiar with the main concepts regarding pipelining, out-of-order execution, cache memories, and virtual memory. Table of Contents: Introduction / Caches / The Instruction Fetch Unit / Decode / Allocation / The Issue Stage / Execute / The Commit Stage / References / Author Biographies

Customers reviews

Frequently Asked Questions about the Book

All books in our catalog are Original.
The book is written in English.
The binding of this edition is Paperback.

Questions and Answers about the Book

Do you have a question about the book? Login to be able to add your own question.

Opinions about Bookdelivery

More customer reviews