Name: VLSI Chip Design Using High Speed ATM Switch
SKU: 58436496
Price: 2918.00 TWD
Availability: InStock
Author: Jain, Manish
ISBN: 9786205527054

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portada VLSI Chip Design Using High Speed ATM Switch

VLSI Chip Design Using High Speed ATM Switch

Type

Physical Book

Author

Manish Jain

Publisher

LAP Lambert Academic Publishing

Language

English

Pages

168

Format

Paperback

Dimensions

22.9x15.2x1 cm

Weight

0.25 kg.

ISBN13

9786205527054

Synopsis "VLSI Chip Design Using High Speed ATM Switch"

This new design is known as the High Performance (HiPer) Switch Architecture. The presentation of the engineering is reproduced utilizing a C++ model. Reenactment results for a haphazardly appropriated traffic design with a 90% likelihood of cells showing up in a schedule opening produces a Cell Loss Ratio of 1.0x 10-8 with yield buffers that can hold 64 cells. The gadget is then modeled in VHDL to confirm its usefulness. At long last the design of a 8x8 switch is delivered utilizing a 0.5 μm CMOS VLSI cycle and reenactments of that circuit show that a pinnacle throughput of 200 Mbps per yield port can be accomplished. An ATM network must oversee traffic reasonably and give viable designation of organization assets for various applications like voice, video and information and give savvy tasks comparative with the quality of service (QOS) specified by the client. The administration of multi-application traffic requires some traffic and clog control methodologies.

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VLSI Chip Design Using High Speed ATM Switch - Jain, Manish

Synopsis "VLSI Chip Design Using High Speed ATM Switch"

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